The present invention relates to semiconductor devices and in particular to a technology effectively applicable to semiconductor devices such as SOC (System On Chip).
Japanese Unexamined Patent Publication No. 2005-259879 (Patent Document 1) discloses a technique wherein the following can be implemented: a burden on layout design can be reduced when a switch is placed in a power supply line for leakage current prevention and the influence of voltage drop that occurs in the switch on signal delay can be reduced.
More specific description will be given. Multiple power supply line groups are disposed in a stripe pattern, and power is supplied to a circuit cell by multiple branch line groups branched from the power supply line groups. Power supply to the circuit cell is interrupted by a power switch cell placed in the branch line groups. For this reason, it is possible to dispersedly dispose power switch cells throughout a region where circuit cells can be disposed and elaborately carry out the interruption of power supply by a power switch cell with respect to each relatively small number of circuit cells.
Japanese Unexamined Patent Publication No. 2005-268695 (Patent Document 2) discloses a technique that provides a function of interrupting power supply to a circuit cell and yet makes it possible to make design more efficient.
More specific description will be given. Multiple power supply line groups are disposed in a vertically-striped pattern at intervals equal to or smaller than a predetermined maximum interval. Multiple branch line groups are branched from the power supply line groups and are disposed in a horizontally-striped pattern within a range from a power supply line group from which they are branched to the next power supply line group. A power switch cell for interrupting power supply from the power supply line groups to the branch line groups is disposed at branch points between the power supply line groups and the branch line groups. Circuit cells supplied with power from the branch line groups are disposed along the branch line groups.
Japanese Unexamined Patent Publication No. 2005-286082 (Patent Document 3) discloses a semiconductor chip in which a power switch controller, a switch cell, a power supply wire, a GND wire, and the like are dispersedly disposed.
Japanese Unexamined Patent Publication No. 2005-159348 (Patent Document 4) and Japanese Unexamined Patent Publication No. Hei 11 (1999)-87520 (Patent Document 5) disclose techniques for disposing a pad in a core region of a semiconductor chip.
[Patent Document 1]
Japanese Unexamined Patent Publication No. 2005-259879
[Patent Document 2]
Japanese Unexamined Patent Publication No. 2005-268695
[Patent Document 3]
Japanese Unexamined Patent Publication No. 2005-286082
[Patent Document 4]
Japanese Unexamined Patent Publication No. 2005-159348
[Patent Document 5]
Japanese Unexamined Patent Publication No. Hei 11(1999)-87520